A liquid crystal display device includes a source driver circuit and a gate driver circuit as driving circuits for driving a display panel. For these driving circuits, a shift register is used for generating a drive signal which controls a drive timing of the display panel. An example of such a shift register is illustrated in FIG. 12.
A shift register 101 as illustrated in FIG. 12 includes a set/reset type flip-flop 102 (102-1, 102-2, . . . ) and a CMOS analog switch 103 (103-1, 103-2, . . . ) in each stage. In addition, the shift register 101 is arranged so that it receives a start pulse SP and two clock signals CK and CKB. The two clock signals CK and CKB have different phases to each other.
The set/reset type flip-flop (hereafter referred as ‘flip-flop’) 102 is set by receiving an active set signal at an S terminal thereof. This causes an output signal Q (Q1, Q2, . . . ) which is outputted from a Q terminal change to High. The High output state is continuously maintained even if the set signal becomes inactive. The flip-flop 102 resets itself when an R terminal thereof receives an active reset signal, to which the output signal Q changes to Low. The Low output state is continuously maintained until the next active set signal is received, even if the reset signal becomes inactive.
Of each of the flip-flops 102, a flip-flop 102-1 receives the start pulse SP as the set signal. The flip-flop 102-1 is in the first stage of the shift register 101, and illustrated as the leftmost stage in FIG. 12. Each of the flip-flops 102 following the flip-flop 102-1 receive an output signal X (X1, X2, . . . ) from the analog switch 103 which corresponds to a flip-flop 102 preceding that flip-flop 102, respectively. The output signal X from the preceding stage is used as the set signal for that flip-flop 102. In addition, each flip-flop 102 receives an output signal X (X2, X3 . . . ) from the analog switch 103 which corresponds to a flip-flop 102 following that flip-flop 102, respectively. The output signal X from the next stage is used as the reset signal for that flip-flop 102.
Each of the analog switches 103 is ON while the High output signal Q (Q1, Q2, . . . ) is outputted from the corresponding flip-flop 102. Meanwhile, the clock signal CK or CKB is outputted from each analog switch 103 as the output signal X (X1, X2, . . . ). This signal is outputted as the output signal of the shift register 101. Specifically, the analog switches 103 which correspond to the flip-flops 102 of the odd stages output the clock signal CK, and the analog switches 103 which correspond to the flip-flops 102 of the even stages output the clock signal CKB.
The analog switch 103 is formed from a PMOS transistor and an NMOS transistor connected in parallel. An inverter 104 is provided in each analog switch 103, and supplies control signals in complementary levels to gates of the PMOS transistor and the NMOS transistor.
Consequently, the clock signal CK or the clock signal CKB is inputted to the flip-flop 102 of the next stage (the one latter stage). This clock signal CK or CKB is used as the set signal, as above. The clock signal CK or the clock signal CKB is also inputted to the flip-flop 102 of the preceding stage (the one preceding stage). This clock signal CK or CKB is used as the reset signal. Note that the clock signal CK and the clock signal CKB are the output signals X.
In this arrangement, the start pulse SP is inputted to the flip-flop 102-1 of the first stage as the set signal. When the flip-flop 102-1 of the first stage is set by receiving the set signal, an output signal Q1 changes to High.
The High output signal Q1 of the flip-flop 102-1 turns ON an analog switch 103-1 which corresponds to the flip-flop 102-1 of the first stage. Consequently, the analog switch 103-1 outputs the clock signal CK as an output signal X1. This output signal X1 is outputted as the output signal of the first stage of the shift register 101.
In addition, the output signal X1 is inputted to a flip-flop 102-2 of the second stage as the set signal thereof. Note that the output signal X1 is the clock signal CK. Accordingly, the flip-flop 102-2 of the second stage is set in the timing the output signal X1 changes to High. This causes an output signal Q2 to change to High as similar to the above. The High output signal Q2 of the flip-flop 102-2 of the second stage turns ON an analog switch 103-2 which corresponds to the flip-flop 102-2 of the second stage. Consequently, the analog switch 103-2 outputs the clock signal CKB as the output signal X2. This output signal X2 is outputted as the output signal of the second stage of the shift register 101.
The output signal X2 is inputted to a flip-flop 102-3 of the third stage as a set signal thereof, as similar to the above. Note that the output signal X2 is the clock signal CKB. Accordingly, the flip-flop 102-3 of the third stage is set in the timing the output signal X2 changes to High, to which an output signal Q3 changes to High. In addition, the output signal X2 is outputted to the preceding flip-flop 102 as the reset signal. That is, the output signal X2 is outputted to the flip-flop 102-1 of the first stage. The flip-flop 102-1 resets itself in the timing the output signal X2 changes to High. This changes the output signal Q1 to Low. Consequently, the analog switch 103-1 corresponding to the flip-flop 102-1 of the first stage turns OFF.
The set/reset operation of the flip-flops 102 and the ON/OFF operation of the analog switches 103 effected by the set/reset operation of the flip-flops 102, operated in each stage, enables the output of the output signals X (X1, X2, . . . ) from the shift register 101. The output signals X have the same width as the clock signals CK and CKB, and do not overlap with each other.
However, the above arrangement of the shift register 101 has a problem in that race hazard would possibly occur in the shift register 101 if a phase lag existed between the clock signals CK and CKB.
The race hazard is explained with reference to FIG. 13. FIG. 13 is a timing chart illustrating the operation of the shift register 101, in the case where a phase lag exists between the clock signals CK and CKB. The phase is lagged to which the phase of the clock signal CKB is delayed with respect to the phase of the clock signal CK.
A rise (A) of the start pulse SP sets the flip-flop 102-1 of the first stage. This changes the output signal Q1 to High. The analog switch 103-1 which corresponds to the flip-flop 102-1 of the first stage turns ON while the output signal Q1 is High. Thus, the clock signal CK is outputted as the output signal X1. The output signal X1 is inputted to the flip-flop 102-2 of the second stage as the set signal. Thus, the flip-flop 102-2 of the second stage is set when the output signal X1 is at a rise (B). Consequently, the output signal Q2 changes to High.
However, since the phase of the clock signal CKB is lagged with respect to the phase of the clock signal CK, there is a period where both the clock signal CK and the clock signal CKB are High. The existence of this period results in output of a superfluous pulse PP as the output signal X2, before a proper pulse PPP of the clock signal CKB is outputted. The superfluous pulse PP outputted as the output signal X2 is equivalent to the amount of delay (lag) in the clock signal CKB is outputted. Because the output signal X2 is the set signal for the flip-flop 102-3 of the third stage, the flip-flop 102-3 is set at a timing (C) with the superfluous output signal X2, even though properly the flip-flop 102-3 should be set at a timing (D).
As a result of the above, an analog switch 103-3 which corresponds to the flip-flop 102-3 of the third stage outputs a High output signal X3 at the same timing as the output signal X1. This causes the flip-flops 102 in the third stage and the latter stages to be set all at the same time. Therefore, the shift register 101 is unable to operate properly, thereby causing the race hazard of the shift register 101.
The phase lag between the clock signals CK and CKB would also be generated while the clock signals CK and CKB are transmitted within the shift register 101.
Patent Document 1 is one technology to prevent such race hazard. A shift register described in Patent Document 1 is as illustrated in FIG. 14.
A shift register 201 as illustrated in FIG. 14 includes a flip-flop section 202 and a race hazard preventing section 203. The flip-flop section 202 has a set/reset type flip-flop 21 (21-1, 21-2, . . . ) on each stage. The race hazard preventing section 203 has a race hazard preventing circuit 22 (22-1, 22-2, . . . ) on each stage. Specifically, each of the stages in the shift register 201 has the set/reset type flip-flop (hereafter referred as simply ‘flip-flop’) 21, and corresponding to each of the flip-flops 21, one race hazard preventing circuit 22 is provided per stage. The race hazard preventing circuit 22 receives an output signal Q (Q1, Q2, . . . ) of the flip-flops 21, respectively. The shift register 201 is arranged so that it receives a start pulse SP and two clock signals CK and CKB. The two clock signals CK and CKB have different phases to each other.
The flip-flop 21-1, which is in the first stage of the flip-flop section 202 illustrated as the leftmost stage in FIG. 14, receives the start pulse SP. In response to the input of the start pulse SP to the flip-flop 21-1, the flip-flop section 202 outputs the output signals Q (Q1, Q2, . . . ) from the flip-flops 21 sequentially in order from the flip-flop 21 on the left end.
The set/reset type flip-flop 21 is set by receiving an active set signal at an S terminal thereof. This causes an output signal Q (Q1, Q2, . . . ) which is outputted from a Q terminal change to High. The High output state is continuously maintained even if the set signal becomes inactive. The flip-flop 21 resets itself when an R terminal thereof receives an active reset signal, to which the output signal Q changes to Low. The Low output state is continuously maintained until the next active set signal is received, even if the reset signal becomes inactive.
Of each of the flip-flops 21, the flip-flop 21-1 receives the start pulse SP as the set signal. The flip-flop 21-1 is illustrated as the leftmost stage in FIG. 14. Each of the flip-flops 21 following the first stage receives an output signal X (X1, X2, . . . ) from the race hazard preventing circuit 22 preceding that flip-flop 21 (corresponding race hazard preventing circuit 22), respectively. The output signal X from the preceding stage is used as the set signal for that flip-flop 21. The race hazard preventing circuit 22 receives the output signal Q (Q1, Q2, . . . ) from the flip-flop 21 of its stage, respectively. In addition, each of the flip-flops 21 receives the output signals X (X1, X2, . . . ) from the race hazard preventing circuit 22 which corresponds to a flip-flop 21 of the next stage, respectively. The output signal X from the next stage is used as the reset signal for that flip-flop 21.
The race hazard preventing section 203 prevents the shift register 201 from race hazard, even if a phase lag exists between the clock signal CK and the clock signal CKB. The existence of the phase lag creates a period where both the clock signal CK and the clock signal CKB to are High, overlappingly The race hazard preventing circuit 22 includes a phase difference detecting section 23 (23a, 23b) and a waveform timing shaping section 24 (24a, 24b).
The phase difference detecting section 23 generates an overlap-removed clock signal by removing an overlapping part of a waveform from the waveform of the clock signal (CK or CKB) which is to be inputted to the flip-flop 21 of the next stage. The overlapping part indicates a period where the waveforms of the clock signals CK and CKB overlap with each other. In the embodiment, the phase difference detecting section 23 detects the waveforms of the clock signal CK and the clock signal CKB, extracts the waveforms of the clock signal CK and the clock signal CKB where there is no overlapping period in the waveforms, and generates a new clock signal (overlap-removed clock signal) from the extracted waveforms.
The phase difference detecting section 23 generates different overlap-removed clock signals in the odd stages and the even stages. The phase difference detecting section 23a for the odd stages outputs output signals A1, A3, . . . as the overlap-removed clocked signal for the odd stages. The output signals A1, A3, . . . are signals in which a lagged part is removed from the clock signal CK (see FIG. 15). The lagged part indicates a part where both the clock signals CK and CKB are High. The phase difference detecting section 23b for the even stages outputs output signals A2, A4, . . . as the overlap-removed clock signal for even stages. The output signals A2, A4, . . . are signals in which the lagged part is removed from the clock signal CKB (see FIG. 15). The generation of new clock signals allows the output signals A1, A3, . . . and the output signals A2, A4, . . . to be signals that do not have the High periods overlapping with each other (see FIG. 15).
These phase difference detecting sections 23a and 23b may be formed from a NOR circuit NOR 1 and an inverter INV 1, as illustrated in FIG. 14. In this case, in the phase difference detecting section 23a of the odd stages, the clock signal CKB is directly inputted to the NOR circuit NOR 1, and the clock signal CK is inversely inputted via the inverter INV1. Thus, the NOR circuit NOR 1 outputs the High signal while the clock signal CK is High and the clock signal CKB is Low. This signal is outputted as the output signals A1, A3, (see FIG. 15).
The phase difference detecting section 23b of the even stages is opposite of that of the odd stages. Namely, the clock signal CK is directly inputted to the NOR circuit NOR 1, and the clock signal CKB is inversely inputted to the NOR circuit NOR 1 via the inverter INV 1. Thus, the NOR circuit NOR 1 outputs the High signal while the clock signal CK is Low and the clock signal CKB is High. This signal is outputted as the output signals A2, A4, . . . (see FIG. 15).
Consequently, as seen in FIG. 15, the output signals A1, A3, . . . and the output signals A2, A4, . . . include an interval between the High periods of each signal. The length of the interval is equivalent to the length of the lag occurred between the clock signals CK and CKB.
A waveform timing shaping section 24 generates output signals X (X1, X2, . . . ) by extracting a period where the output signals A (A1, A2, . . . ) is High, while the output signal Q (Q1, Q2, . . . ) of the corresponding flip-flop 21 is High. The output signals A are the overlap-removed clock signals generated in the phase difference detecting sections 23. The output signals X are outputted as the set signal for the following flip-flops 21, respectively. The arrangements of the waveform timing shaping section 24 of the odd stages and the even stages are the same.
In addition, the output signals X (X1, X2 . . . ) of each of the waveform timing shaping sections 24 is outputted as the output signal of the shift register 201. The output signal X of each of the waveform timing shaping sections 24 also is inputted to the flip-flop 21 of the preceding stage. The output signal inputted to the preceding flip-flop 21 is used as the reset signal, which resets the preceding flip-flop 21.
The waveform timing shaping section 24 may be formed including a NAND circuit NAND 1 and an inverter INV 2, as illustrated in FIG. 14. The NAND circuit NAND 1 receives the output signals A (A1, A2, A3, . . . ) from the corresponding phase difference detecting section 23, and receives the output signals Q (Q1, Q2, Q3, . . . ) from the corresponding flip-flop 21. An output signal from the NAND circuit NAND 1 is inverted via the inverter INV 2. The inverted output signal is outputted as the output signals X (X1, X2, . . . ). The NAND circuit NAND 1 has a Low output when both the output signals A and the output signals Q, each of which are to be inputted to the NAND circuit NAND 1, are in the High period. Because the output signal from the NAND circuit NAND 1 is inverted via the inverter INV 2, the waveform timing shaping section 24 outputs the High output signal X (X1, X2, . . . ) when both the output signals A and output signals Q are in the High period (see FIG. 15).
The following description deals with an operation of the shift register 201, with reference to a timing chart in FIG. 15. The flip-flop 21-1 of the first stage is set (a) when the start pulse SP is inputted thereto as the set signal. This changes the output signal Q1 to High.
In response to a High output signal Q1 from the flip-flop 21-1, the race hazard preventing circuit 22-1, which corresponds to the flip-flop 21-1 of the first stage, outputs an output signal X1. More precisely, the output signal X1 is outputted from the waveform timing shaping section 24 of the race hazard preventing circuit 22-1. The output signal X1 is High while an output signal A1 generated by the phase difference detecting section 23a in the race hazard preventing circuit 22-1 is High. The output signal X1 is outputted as the output of the first stage of the shift register 201.
The output signal X1 is inputted to the flip-flop 21-2 of the second stage as the set signal thereof. The flip-flop 21-2 of the second stage is set (b) in the timing the output signal X1 changes to High. This causes an output signal Q2 of the flip-flop 21-2 of the second stage to change to High, as similar to the above. In response to a High output signal Q2 of the flip-flop 21-2, the race hazard preventing circuit 22-2, which corresponds to the flip-flop 21-2 of the second stage, outputs an output signal X2. More precisely, the output signal X2 is outputted from the waveform timing shaping section 24b of the race hazard preventing circuit 22-2. The output signal X2 is High while an output signal A2 generated by the phase difference detecting section 23b in the race hazard preventing circuit 22-2 is High. The output signal X2 is outputted as the output of the second stage of the shift register 201.
The output signal X2 is inputted to the flip-flop 21-3 of the third stage as the set signal thereof, as similar to the above. The flip-flop 21-3 of the third stage is set (c) in the timing the output signal X2 changes to High. An output signal X3 which is High while the output signal A3 is High is outputted from the corresponding race hazard preventing circuit 22-3. The output signal X3 is outputted as the output of the third stage of the shift register 201. In addition, the output signal X2 is also inputted to the preceding flip-flop 21-1. The output signal X2 is used as a reset signal for that preceding flip-flop 21-1. That is, the output signal X2 is inputted to the flip-flop 21-1 of the first stage. Thus, the flip-flop 21-1 of the first stage is reset (e) in the timing the output signal X2 changes to High. This causes the output signal Q1 to change to Low.
The output signal X3 is inputted to a flip-flop 21-4 of the fourth stage as the set signal thereof, as similar to the above. Thus, the flip-flop 21-4 of the fourth stage is set (d) in the timing the output signal X3 changes to High. In addition, the output signal X3 is also inputted to the preceding flip-flop 21-2. The output signal X3 is used as a reset signal for that preceding flip-flop 21-2. That is, the output signal X3 is inputted to the flip-flop 21-2 of the second stage. Therefore, the flip-flop 21-2 of the second stage is reset (f) in the timing the output signal X3 changes to High.
The set/reset operation of the flip-flops 102 and the output operation of the output signals X (X1, X2, . . . ) by the race hazard preventing circuit 22, each successively operated in the stages of the shift register 201, enables the output of the output signals X (X1, X2, . . . ) which do not overlap with each other from the shift register 201. Specifically, the output signals X which do not overlap with each other are outputted as a result of the following process. The output signals X1, X3, . . . are outputted from the odd stages of the shift register 201. The output signals X1, X3, . . . use the High periods of the output signals A1, A3, . . . . The output signals A1, A3, . . . are overlap-removed clock signals for the odd stages. On the other hand, the output signals X2, X4, . . . are outputted from the even stages of the shift register 201. The output signals X2, X4, . . . use the High periods of the output signals A2, A4, . . . . The output signals A2, A4, . . . are overlap-removed clock signals for the even stages in which the High period thereof do not overlap with the High period of the output signals A1, A3, . . . .
As such, the shift register 201 can properly operate having no race hazard occurring by using the output signals X (X1, X2, . . . ) as the set signal for the flip-flop 21 of the next stage, even if a phase lag occurs in the clock signals CK and CKB.
Patent Document 1
    Japanese Unexamined Patent Publication, Tokukai, No. 2005-222655 (published on Aug. 18, 2005))Patent Document 2    Japanese Unexamined Patent Publication, Tokukai, No. 2004-126551 (published on Apr. 22, 2004)Patent Document 3    Patent No. 3536657 (registered on Mar. 26, 2004, Japanese Unexamined Patent Publication, Tokukaihei, No, 11-282397 (published on Oct. 15, 1999))Patent Document 4
Japanese Unexamined Patent Publication, Tokukaihei, No. 5-2889 (published on Jan. 8, 1993)